0.6um 1p2mcmos process platform。0.6um gate length，single poly, double metal， application for power management product，core/io voltage：5.0v, （24v optional）。fmic has the elaborate design rule document.
process features
ø single poly, double metal, twin well.
ø core/io voltage：5.0v, vds>5v, vgs>5v. （24v optional）
ø substrate silicon material is p-type <100>, 15-25ohm-cm.
ø 11 masks and 13 photo layers.
ø n-type mask rom code for option.
ø standard locos process for isolation.
ø 150a gate oxide, poly for gate electrode.
ø nldd, pldd and spacer structure.
ø ti/tin/alsicu/tin stack layer for interconnection.
ø oxide and nitride stack layer for passivation.
ø imd planarization process.
applications
ø dc-dc converter
ø power management product
ø battery protection ic
ø led driver